A semiconductor memory element, such as a flash memory, may include excellent sensing characteristics, and may have a low bit line resistance. A lower resistance of an interconnection may improve process coverage in a design by increasing the signal process speed and improving the sensing margin.
As semiconductor techniques develop, a size of cells may be reduced. However, a resistance of the interconnection may limit how small a cell size can be reduced. Accordingly it may be important to improve the resistance of the interconnection.
Copper may be used as an interconnection material in an effort to improve the resistance. Since a copper interconnection may have a low specific resistance as compared to an aluminum interconnection, the copper interconnection may be effective to solve a resistance problem of interconnections.
However, since copper interconnection techniques may be more expensive, a product yield may be degraded if the copper interconnection technique is applied to memory products.
A related art metal interconnection structure is shown in FIG. 1.
Referring to FIG. 1, isolation layer 11, which may define an active area, may be formed on silicon substrate 10. Interlayer dielectric 12 may be formed on a surface (for example, the entire surface) of silicon substrate 10.
Contact plug 13, which may be in contact with the active area of silicon substrate 10, may be formed by selectively etching interlayer dielectric 12. Aluminum interconnection 14 may be formed on contact plug 13.
In the metal interconnection structure, since a margin of space may be small, it may be difficult to control a process. Accordingly a change of contact resistance may occur due to a misalignment between aluminum interconnection 14 and contact plug 13.
Moreover, since the metal interconnection structure may have a large aspect ratio due to a shallow gap between aluminum interconnection 14, a void may be caused by not filling the gap between aluminum interconnection 14 if an interlayer dielectric is deposited in a subsequent process.
This may affect a thickness of the interconnection. Accordingly, if a size of cells is reduced, a problem with the interconnection resistance may occur.